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ISL55020
Data Sheet December 18, 2006 FN6287.0
Wideband, Low Distortion, Differential Amplifier
The ISL55020 is fully differential wideband amplifier designed to drive differential ADCs. This device features a high drive capability of 100mA, low operating quiescent current of 21mA and operates with both single and dual supplies over a range of 4.5V (2.25V) to +12V (6V). Key features include high impedance, full differential inputs and full differential or DC referenced complementary singleended outputs A wide bandwidth unity gain common mode (VCM) amplifier input is included to provide DC offset correction or common mode signal injection to the differential output. The ISL55020 is available in the thermally-enhanced 16 Ld QFN package and is specified for operation over the full -40C to +85C temperature range. The ISL55020 has an EN pin to disable the outputs.
Features
* Fully differential current feedback amplifier * High impedance differential inputs * Differential output drives up to 100mA from a +12V supply * Separate unity-gain common mode input (VCM) * 300MHz bandwidth * 1200V/s Slewrate * -73.3dBc typical driver output distortion at 10VPP; 1MHz * -64.6dBc typical driver output distortion at 10VPP; 4MHz * Low quiescent supply current of 21mA * Pb-free plus anneal available (RoHS compliant)
Applications
* High Linearity ADC preamplifier * Differential driver
Ordering Information
PART NUMBER (Note) ISL55020IRZ PART MARKING 55020IRZ TAPE & REEL 13" PACKAGE (Pb-Free) PKG. DWG. #
* Wireless communication receiver * Differential active filter
16 Ld QFN MDP0046 16 Ld QFN MDP0046
ISL55020IRZ-T13 55020IRZ
Pinout
ISL55020 (16 LD QFN) TOP VIEW
OUT+ OUT13 12 NC + 11 FBNC 15
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
NC 1 FB+ 2 IN+ 3 GND 4
16
14
V+
+1
+ 10 IN9 NC 5 VCM 6 NC 7 V8 EN
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2006. All Rights Reserved. Elantec is a registered trademark of Elantec Semiconductor, Inc. All other trademarks mentioned are the property of their respective owners.
ISL55020
Absolute Maximum Ratings (TA = +25C)
V+ Voltage to Ground or V- . . . . . . . . . . . . . . . . . . . -0.3V to +13.2V V- Voltage to Ground or V+ . . . . . . . . . . . . . . . . . . . +0.3V to -13.2V IN+, IN-, FB+, FB-, VCM, EN Voltage . . . . . . . V- -0.3V to V+ +0.3V Current into any Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8mA Continuous Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . 100mA ESD Tolerance Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3kV Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200V
Thermal Information
Thermal Resistance JA (C/W) 16 Ld QFN Package . . . . . . . . . . . . . . . . . . . . . . . . 40 Ambient Operating Temperature Range . . . . . . . . . .-40C to +85C Storage Temperature Range . . . . . . . . . . . . . . . . . .-60C to +150C Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +150C
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications
PARAMETER DC PERFORMANCE VOS VOS
VS = 12V, RF = 750, RG = 1.5k, RL = 1k connected to mid supply, TA = +25C, unless otherwise specified. DESCRIPTION CONDITIONS MIN TYP MAX UNIT
Common Mode Offset Voltage VOS Mismatch
-38 -7
15 0.7
38 7
mV mV
INPUT CHARACTERISTICS IB+, IBFB+, FBIBeN Non-Inverting Input Bias Current Inverting Input Bias Current IB- Mismatch Input Noise Voltage fo = 1kHz fo = 10kHz iN Input Noise Current fo = 1kHz fo = 10kHz CMIR VCM IB VCM VOS VCM VCM Av CMIR VCM Input Bias Current ((VOUT+) + (VOUT -))/2 Close Loop Gain Common Mode Input Range VCM VCM = 5V to 6V VCM, IN +, IN- = 0V, RL = 1k VCM = 1V, VCM = 5V to 6V -7 -150 0.87 2.3 0.95 7 150 1.03 9.7 A mV V/V V Common Mode Input Range IN+, IN2 -7 -125 -75 25 0 9.8 6.9 6.6 2.7 10 7 125 75 A A A nV Hz nV Hz pA/ Hz pA/ Hz V
OUTPUT CHARACTERISTICS VOUT Loaded Output Swing (differential) VS = 6V, RL = 1k differential load VS = 4.5V, RL = 1k differential load IOUT Output Current RL = 0 differential load RL = 50 differential load SUPPLY VS IS+ ENABLE IS- ENABLE IS+ DISABLE IS- DISABLE Ts Ts-hys Supply Voltage Positive Supply Current Negative Supply Positive Supply Current Negative Supply Thermal Shutdown Temperature Thermal Shutdown Hysteresis Single supply All outputs at 0V, EN = 0V All outputs at 0V, EN = 0V All outputs at 0V, EN = 5V All outputs at 0V, EN = 5V IC Junction Temperature IC Junction Shutdown Hysteresis 4.5 14 -28 0.5 -2.5 21 -21 1.4 -1.6 185 15 12 28 -14 2.5 0.5 V mA mA mA mA 1.45 4.8 1.05 150 5.0 V V mA mA
C C
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FN6287.0 December 18, 2006
ISL55020
Electrical Specifications
PARAMETER LOGIC VINH, EN VINL, EN IINH, EN IINL, EN tEN ON tEN OFF RIN ENABLE High Level ENABLE Low Level Input Current, High Input Current, Low Enable time, off to on Disable time, on to off ENABLE = 5V ENABLE = 0V ENABLE = 5V to 0V ENABLE = 0V to 5V 1 1 180 -5 12 250 250 2 0.8 320 +5 V V A A nS nS M M VS = 12V, RF = 750, RG = 1.5k, RL = 1k connected to mid supply, TA = +25C, unless otherwise specified. (Continued) DESCRIPTION CONDITIONS MIN TYP MAX UNIT
IN+, IN- Input resistance disables state V+ = 12V, Vin = 2V to 10V, ENABLE = 5V V+ = 4.5V,Vin = 2V to 4V, ENABLE = 5V
AC PERFORMANCE BW -3dB Bandwidth, single-ended output to AVS = +2.5, RF = 750, RG = 374, RL=100 GND (Figure 3) AVS = 5, RF = 750, RG = 169, RL=100 THD, HD2, HD3 THD, A = 2; Differential f = 1MHz, VO = 1VP-P, RL = 1k f = 1MHz, VO = 10VP-P, RL = 1k f = 4MHz, VO = 1VP-P, RL = 1k f = 4MHz, VO = 10VP-P, RL = 1k HD2, AV = 2; Differential f = 1MHz, VO = 1VP-P, RL = 1k f = 1MHz, VO = 10VP-P, RL = 1k f = 4MHz, VO = 1VP-P, RL = 1k f = 4MHz, VO = 10VP-P, RL = 1k HD3, AV = 2; Differential f = 1MHz, VO = 1VP-P, RL = 1k f = 1MHz, VO = 10VP-P, RL = 1k f = 4MHz, VO = 1VP-P, RL = 1k f = 4MHz, VO = 10VP-P, RL = 1k SR Slew Rate, Single-ended VOUT from -3V to +3V, RL = 1k 600 300 200 -63.8 -73.3 -57.4 -62.4 -82.3 77.6 -62.3 -64.6 -68.5 -83.5 -60.3 -67.7 1200 MHz MHz dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc V/s
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FN6287.0 December 18, 2006
ISL55020 Typical Performance Curves
1 0 NORMALIZED GAIN (dB) -1 -2 -3 -4 -5 -6 -7 -8 AVS = 2.5 RIN = 200 RF = 750 RG = 374 VOUT = 100mVP-P 1M 10M FREQUENCY (Hz) RL = 500 RL = 250 RL = 1000 NORMALIZED GAIN (dB) 16 14 12 10 8 6 4 2 0 -2 AVS = 2.5 -4 R = 200 IN -6 RF = 750 -8 -10 RG = 374 -12 RL = 100 -14 VOUT = 100mVP-P -16 100k 1M CL = 24.3pF CL = 2.3pF
CL = 14.4pF CL = 9.1pF CL = 2.3pF
RL = 100 RL = 50 100M 1G
-9 100k
10M
100M
1G
FREQUENCY (Hz)
FIGURE 1. SINGLE-ENDED GAIN vs FREQUENCY vs RL
FIGURE 2. SINGLE-ENDED GAIN vs FREQUENCY vs CL
40 35 30 GAIN (dB) 25 20 15 10 5 AVS = 2.5, RF = 750, RG = 374 1M 10M FREQUENCY (Hz) 100M 1G AVS = 5, RF = 750, RG = 169 AVS = 50, RF = 750, RG = 15.4 RIN = 200 RL = 100 VOUT = 100mVP-P
5 4 NORMALIZED GAIN (dB) 3 2 1 0 -1 -2 -3 -4 AVS = 2.5 RIN = 200 RF = 750 RG = 374 RL = 100 to GND VOUT = 100mVP-P 1M 10M FREQUENCY (Hz) VS = 6 VS = 3 VS = 2.25
0 100k
-5 100k
100M
1G
FIGURE 3. CLOSED LOOP GAIN vs FREQUENCY
FIGURE 4. SINGLE-ENDED GAIN vs FREQUENCY vs VS
12 10 NORMALIZED GAIN (dB) 8 6 4 2 0 -2 -4 -6 -8 AVS = 2.5 RL= 100 VOUT = 100mVP-P 1M RF = 750, RG = 374 RF = 374, RG = 187 RF = 187, RG = 93.1 NORMALIZED GAIN (dB)
1 0 -1 -2 -3 -4 -5 -6 -7 -8 1G INPUT = VCM AVCM = 1 AVS = 2.5 RIN = 200 RF = 750 RG = 374 VOUT = 100mVP-P 1M 10M FREQUENCY (Hz) 100M
RL = 50 RL = 100 RL = 250 RL = 500 RL = 1000
RF = 1500, RG = 750 10M FREQUENCY (Hz) 100M
-10 100k
-9 100k
1G
FIGURE 5. SINGLE-ENDED GAIN vs FREQUENCY vs RF/RG
FIGURE 6. VCM GAIN vs FREQUENCY vs RL
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FN6287.0 December 18, 2006
ISL55020 Typical Performance Curves (Continued)
1 0 NORMALIZED GAIN (dB) -1 -2 -3 -4 -5 -6 -7 -8 INPUT = VCM AVCM = 1 AVS = 2.5 RIN = 200 RF = 750 RG = 374 RL = 100 VOUT = 100mVP-P 1M CL = 14.4pF PSRR+ (dB) CL = 24.3pF 10 0 -10 -20 -30 -40 -50 CL = 2.3pF 10M FREQUENCY (Hz) 100M 1G -60 100k VS = 3V VS = 6V 1M 10M FREQUENCY (Hz) 100M 1G AVS = 2.5 RIN = 200 RF = 750 RG = 374 RL = 100 VPSRR = 1VP-P
VS = 2.25V
CL = 9.1pF
-9 100k
FIGURE 7. VCM GAIN vs FREQUENCY vs CL
FIGURE 8. PSRR+ vs FREQUENCY vs VS (DUAL SUPPLIES)
PSRR- (dB)
PSRR+ (dB)
AVS = 2.5 0 RIN = 200 RF = 750 -10 RG = 374 RL = 100 -20 VPSRR = 1VP-P -30 -40 -50 VS = 2.25V -60
VS = 3V
10
20 VS = 2.25V VPSRR = 500mVP-P 10 0 -10 AVS = 2.5 RIN = 200 RF = 750 RG = 374 RL = 100 VPSRR = 1VP-P
VS = +4.5V -20 VCM = 2.25V -30
VS = 6V 1M 10M FREQUENCY (Hz) 100M 1G
-40 -50 100k 1M 10M FREQUENCY (Hz) 100M 1G
-70 100k
FIGURE 9. PSRR- vs FREQUENCY vs VS
FIGURE 10. PSRR+ vs FREQUENCY vs VS (SINGLE SUPPLY)
-20 -30 OFF ISOLATION (dB) -40 -50 -60 -70 -80 -90 VCM OFF ISOLATION (dB) AVS = 2.5 RIN = 200 RF = 1500 RG = 374 RL = 100 VIN = 1VP-P
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 1M 10M FREQUENCY (Hz) 100M 1G -110 100k 1M 10M FREQUENCY (Hz) 100M 1G AVS = 2.5 AVCM = 1 RIN = 200 RF = 1500 RG = 374 RL = 100 VIN = 1VP-P
-100 -110 -120 100k
FIGURE 11. INPUT OFF ISOLATION GAIN vs FREQUENCY SINGLE-ENDED
FIGURE 12. VCM OFF ISOLATION vs FREQUENCY - SINGLEENDED
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FN6287.0 December 18, 2006
ISL55020 Typical Performance Curves (Continued)
0.12 0.10 0.08 VOUT (V) 0.06 0.04 0.02 0 -0.02 0 5 10 15 VOUT (V) AVS = 2.5 VS = 6V RL = 100 TO GND 20 25 30 35 40 45 50 6 4 2 0 -2 -4 -6 AVS = 2.5 VS = 6V RL = 100 TO GND 0 50 100 150 200 250 TIME (ns) 300 350 400
TIME (ns)
FIGURE 13. SMALL SIGNAL STEP RESPONSE
FIGURE 14. LARGE SIGNAL STEP RESPONSE
0.12 0.10 0.08 VOUT (V) AVS = 2.5 VS = 6V RL = 100 TO GND 0 5 10 15 20 25 30 35 40 45 50 VOUT (V) 0.06 0.04 0.02 0 -0.02
3 2 1 0 -1 -2 -3 -4 0 50 100 AVS = 2.5 VS = 6V RL = 100 TO GND 150 200 250 300 350 400 TIME (ns)
TIME (ns)
FIGURE 15. SMALL SIGNAL STEP RESPONSE - VCM TO VOUT
FIGURE 16. LARGE SIGNAL STEP RESPONSE - VCM TO VOUT
2.1 V-ENABLE (V) 1.8 1.5 VOUT (V) 1.2 0.9 0.6 0.3 0 0 100 200 300 VOUT (V) 400 500 TIME (ns) 600 700 AVS = 2.5 VS = 6V RL = 100 TO GND
6 5 4 3 2 1 0 -1 800
FIGURE 17. ENABLE TO OUTPUT DELAY
6
V-ENABLE (V)
FN6287.0 December 18, 2006
ISL55020 Pin Descriptions
PIN NUMBER 1, 6, 9, 12, 15 2 3 4 5 7 8 10 11 13 14 16 Thermal Pad PIN NAME NC FB+ IN+ GND VCM VEN INFBOUTV+ OUT+ Circuit1 Circuit 1 Circuit 4 Circuit 1 Circuit 4 Circuit 2 Circuit 1 Circuit 1 Circuit 3 Circuit 4 Circuit 3 Circuit 5 EQUIVALENT CIRCUIT PIN FUNCTION No connect; grounded for best AC performance Feedback from non-inverting output Non-inverting input Ground Reference input, sets common-mode output voltage with AV = 1. Must be st to V+/2 for single supply applications Negative supply. Must be connected to GND for single supply operation Enable pin with internal pull-down; Logic "1" selects the disabled state; Logic "0" selects the enabled state Inverting input Feedback from inverting output Inverting output Positive supply Non-inverting output Pack thermal pad electrically connected to IC substrate - must be connected to most negative voltage applied to the IC
V+ EN GND VCIRCUIT 2 CIRCUIT 3 V+ OUT V-
V+ IN+, INVCM VFB+,FB-
CIRCUIT 1
V+ GND VCIRCUIT 4.
CAPACITIVELY COUPLED ESD CLAMP
THERMAL HEAT SINK PAD ~1M VSUBSTRATE CIRCUIT 5
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FN6287.0 December 18, 2006
ISL55020
V+ V-
RF1
VIN+ RT+ VINRTVCM RT-VCM EN RG
RIN+
FB+ IN+
V+
V-
OUT+
RS+ RL+ RS+ RLVOUT VOUT+
VCM +1 RININFBGNDOUTEN
RF2
GND-
FIGURE 18. BASIC APPLICATION CIRCUIT
Description of Operation and Application Information
Product Description
The ISL55020 is a full differential Current Feedback Amplifier (CFA) featuring wide bandwidth and low power. The device contains a pair of high impedance differential inputs and a pair of differential outputs. It can be used in any combination of single/differential ended input/output configurations. A wide bandwidth unity gain, common mode amplifier with a 100MHz -3dB bandwidth (Figure 6) is included to provide DC offset correction or common mode signal injection to the differential output. The ISL55020 is internally compensated for single-ended closed loop gain (AVS), differential closed gain (AVD) of 2, or greater. Connected in differential gain of 5 (single ended gain of 2.5 and driving a 200 differential load, the ISL55020 has a 3dB bandwidth of 300MHz. Driving a 200 differential load at gain of 10, the bandwidth is about 200MHz (Figure 3). The ISL55020 is available with a power down feature (EN) to reduce the power while the amplifier is disabled.
mode signal is outside the above-specified ranges, the output signal will be distorted. The output of the ISL55020 can swing from -3.8V to +3.8V at 100 differential load at 5V supply. As the load resistance becomes lower, the output swing is reduced.
Single-ended, Differential and Common Mode Gain Settings
The ISL55020 can be used as a single/differential ended to differential/single converter. The voltage applied at VCM pin sets the output common mode voltage and the common mode gain is fixed at gain is one (AVCM = 1). The output differential voltage is given by the following:
VOD = (VIN+ - VIN-) x (1 + 2RF/RG) (EQ. 1)
Where: RF1 = RF2 = RF The differential output gain (AVD) is defined by the feedback resistors according to the following
AVD = 1 + 2RF/RG (EQ. 2)
Input, Output, and Supply Voltage Range
The ISL55020 is designed to operate with dual supplies over a range of +/-2.25V to +/-6V and can also operate with a single supply over the range of 4.5V to 12V. For single supply operation, the V- and GND pins must be connected together as close to the device as possible. The amplifiers have an input common mode voltage range from -4.3V to 3.4V when operated from 5V supplies. The differential mode input range (DMIR) between the two inputs is from 2.3V to +2.3V. The input voltage range at the VCM pin is from -3.3V to 3.7V. If the input common mode or differential
The single ended output voltage (VOS) contains a common mode component (VCM) and a differential mode component equal to one-half the differential output (VOD/2)., and is given by the following:
VOS = VOD/2 + VCM = VCM +(VIN+ - VIN-) x (0.5 + RF/RG) (EQ. 3)
and the single-ended gain becomes:
AVS = 0.5+ RF/RG (EQ. 4)
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FN6287.0 December 18, 2006
ISL55020
Feedback Resistor, Gain Bandwidth Product and Stability Considerations (See Figure 18 - Basic
Application Schematic)
Output Drive Capability
The ISL55020 has no internal current-limiting circuitry. If the output is shorted, it is possible to exceed the Absolute Maximum Rating for output current or power dissipation, potentially resulting in the destruction of the device.internal short circuit protection.
For gains greater than 1, the feedback resistor forms a pole with the parasitic capacitance at the inverting input. As this pole becomes lower in frequency, the amplifier's phase margin is reduced. Excessive parasitic capacitance at the input will cause excessive ringing in the time domain and peaking in the frequency domain. High feedback resistor values have the same effect, and therefore should be kept as low as possible. Figure 5 shows the gain-peaking effect of using higher feedback resistor values. Feedback resistor RF has some maximum value that should not be exceeded for optimum performance. Unlike voltage feedback (VFA) amplifier topologies that exhibit constant gain-bandwidth product, CFA amplifiers maintain high bandwidth at gains high greater than 1. Figure 3 illustrates the nearly constant bandwidth from a single-ended gain (AVS) of 2.5 to 5, and only a slight reduction out to a AVS of 50. For the gains other than 1, optimum response is obtained with RF between 500 to 1k. The high impedance inputs IN+ and IN- are sensitive parasitic capacitance and inductance. To ensure input stability, a small value resistor (200 recommended) should be placed as close to the device IN+ and IN- pins as possible.
Power Dissipation
With the high output drive capability of the ISL55020, It is possible to exceed the +150C absolute maximum junction temperature under certain load current conditions. Therefore, it is important to calculate the maximum junction temperature for the application to determine if the load conditions or package types need to be modified for the amplifier to remain in the safe operating area. A thermal shutdown circuit is included that implements a thermal shutdown if the junction temperature exceeds ~+185C. The thermal shutdown includes thermal hysteresis of ~+15C. The thermal shutdown feature is designed to protect the device during accidental overload conditions and continuous operation at junction temperatures greater than +150C should never be allowed. The maximum power dissipation allowed in a package is determined according to:
T JMAX - T AMAX PD MAX = ------------------------------------------- JA
Driving Capacitive Loads and Cables
Excessive output capacitance also contributes to gain peaking (Figure 2) and high overshoot in pulse applications. For PC board layouts requiring long traces at the output, a small series resistor (Figure 17 - RS+, RS- usually between 5 to 50) should be inserted as close to the device output pin as possible to each to minimize peaking,. The resultant gain error should be compensated with an appropriate adjustment of RG. When used as a cable driver, double termination is always recommended for reflection-free performance. For those applications, a back-termination series resistor (RS) at the amplifier's output will isolate the amplifier from the cable and allow extensive capacitive drive. However, other applications may have high capacitive loads without a back-termination resistor. Again, a small series resistor at the output can help to reduce peaking.
Where: TJMAX = Maximum junction temperature TAMAX = Maximum ambient temperature JA = Thermal resistance of the package The maximum power dissipation actually produced by an IC is the total quiescent supply current times the total power supply voltage, plus the power in the IC due to the load, or:
V O PD = V S x I SMAX + V S x ----------R
LD
Where: VS = Total supply voltage ISMAX = Maximum quiescent supply current per channel VO = Maximum differential output voltage of the application RLD = Differential load resistance ILOAD = Load current By setting the two PDMAX equations equal to each other, we can solve the output current and RLD to avoid the device overheat.
Disable/Power-Down
The ISL55020 can be disabled with it's outputs in a high impedance state. The turn off time is about 250nS and the turn on time is about 12nS (Figure 17). When disabled, the amplifier's supply current is reduced to 1.4mA for IS+ and 1.6mA for IS- typically. The amplifier's power down can be controlled by standard ground-referenced CMOS signal levels at the EN pin. V.
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FN6287.0 December 18, 2006
ISL55020
Power Supply Bypassing and Printed Circuit Board Layout
As with any high frequency device, a good printed circuit board layout is necessary for optimum performance. Lead lengths should be as sort as possible. The power supply pin must be well bypassed to reduce the risk of oscillation. For normal single supply operation, where the V- pin is connected to the ground plane, a single 4.7F tantalum capacitor in parallel with a 0.1F ceramic capacitor from V+ to GND will suffice. This same capacitor combination should be placed at each supply pin to ground if split supplies are to be used. In this case, the V- pin becomes the negative supply rail. For good AC performance, parasitic capacitance should be kept to minimum. Use of wire wound resistors should be avoided because of their additional series inductance. Use of sockets should also be avoided if possible. Sockets add parasitic inductance and capacitance that can result in compromised performance. Minimizing parasitic capacitance at the amplifier's inverting input pin is very important. The feedback resistor should be placed very close to the inverting input pin. Strip line design techniques are recommended for the signal traces.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 10
FN6287.0 December 18, 2006
ISL55020 QFN (Quad Flat No-Lead) Package Family
A D N (N-1) (N-2) B
MDP0046
QFN (QUAD FLAT NO-LEAD) PACKAGE FAMILY (COMPLIANT TO JEDEC MO-220) SYMBOL QFN44 QFN38 A A1 0.90 0.02 0.25 0.20 7.00 5.10 7.00 5.10 0.50 0.55 44 11 11 0.90 0.02 0.25 0.20 5.00 3.80 7.00 5.80 0.50 0.40 38 7 12 QFN32 0.90 0.02 0.23 0.20 8.00 0.90 0.02 0.22 0.20 5.00 TOLERANCE 0.10 +0.03/-0.02 0.02 Reference Basic Reference Basic Reference Basic 0.05 Reference Reference Reference NOTES 8 8 4 6 5
1 2 3
b
PIN #1 I.D. MARK E
c D D2 E E2
(N/2)
5.80 3.60/2.48 8.00 6.00
5.80 4.60/3.40 0.80 0.53 32 8 8 0.50 0.50 32 7 9
2X 0.075 C
e
2X 0.075 C
L N ND NE
TOP VIEW N LEADS
0.10 M C A B (N-2) (N-1) N b
L
PIN #1 I.D. 3 1 2 3
SYMBOL QFN28 QFN24 A A1 b 0.90 0.02 0.25 0.20 4.00 2.65 5.00 3.65 0.50 0.40 28 6 8 0.90 0.02 0.25 0.20 4.00 2.80 5.00 3.80 0.50 0.40 24 5 7
QFN20 0.90 0.02 0.30 0.20 5.00 3.70 5.00 3.70 0.65 0.40 20 5 5 0.90 0.02 0.25 0.20 4.00 2.70 4.00 2.70 0.50 0.40 20 5 5
QFN16 0.90 0.02 0.33 0.20 4.00 2.40 4.00 2.40 0.65 0.60 16 4 4
TOLERANCE NOTES 0.10 +0.03/ -0.02 0.02 Reference Basic Reference Basic Reference Basic 0.05 Reference Reference Reference 4 6 5
(E2)
c D
NE 5 (N/2)
D2 E E2
(D2) BOTTOM VIEW
7
e L N
e C SEATING PLANE 0.08 C N LEADS & EXPOSED PAD
0.10 C
ND NE NOTES:
Rev 10 12/04 1. Dimensioning and tolerancing per ASME Y14.5M-1994.
SEE DETAIL "X" SIDE VIEW
2. Tiebar view shown is a non-functional feature. 3. Bottom-side pin #1 I.D. is a diepad chamfer as shown. 4. N is the total number of terminals on the device. 5. NE is the number of terminals on the "E" side of the package (or Y-direction).
(c) C A
2
6. ND is the number of terminals on the "D" side of the package (or X-direction). ND = (N/2)-NE.
(L)
7. Inward end of terminal may be square or circular in shape with radius (b/2) as shown. 8. If two values are listed, multiple exposed pad options are available. Refer to device-specific datasheet.
A1 DETAIL X
N LEADS
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FN6287.0 December 18, 2006

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